EP20K200EBC652-3N vs EP20K1500EBC652-1X 对比

详细并排对比 EP20K200EBC652-3N 出自 Altera 和 EP20K1500EBC652-1X 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K200EBC652-3N EP20K1500EBC652-1X
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $220.00 $175.00
Series APEX 20KE (APEX-20KE®) —
Device Family EP20K200 —
System Gates 200,000 1.5 M
Logic Elements / Cells 8,320 51840
Logic Array Blocks (LABs) 832 —
Macrocells 832 —
Embedded RAM 106,496 bits —
User I/Os (DigiKey listing) 376 —
User I/Os (digchip listing) 277 —
Propagation Delay 2.33 ns 1.84 ns
Internal Frequency (max) 189 MHz —
Process Technology 0.22 µm CMOS 0.22 µm CMOS
Core Supply Voltage 1.71 V to 1.89 V (nominal 1.8 V) —
I/O Supply (LVDS-capable) LVDS, 2.5 V referenced (per source variant) —
封装 652-ball BGA 652-ball BGA (FCBGA / PBGA652)
安装类型 Surface Mount Surface Mount
Operating Temperature (TJ) 0 °C to 85 °C (commercial) —
Speed Grade -3 (slowest in APEX 20KE family) —
Configuration JTAG (IEEE 1149.1), Passive Serial —
RoHS 状态 Compliant [DATA_NEEDED: RoHS compliance]
Family — APEX 20KE
Macros — 3456
Total RAM Bits — 442368
User I/O — 488
Number of I/O Banks — [DATA_NEEDED: I/O bank count]
Internal Frequency — 160 MHz (per digchip) / 400 MHz (per fpgakey)
Core Voltage — 1.8 V
工作温度 — 0 °C to +85 °C (commercial)
MSL 等级 — [DATA_NEEDED: MSL rating]
Configuration Method — JTAG / SRAM
Architecture — MultiCore (LUT + product-term)

数据手册与资源

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