EP20K200EFC484-2N vs EP20K200BC484-1X 对比

详细并排对比 EP20K200EFC484-2N 出自 Intel 和 EP20K200BC484-1X 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K200EFC484-2N EP20K200BC484-1X
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $175.00 $75.10
Family APEX-20KE —
Product Type FPGA - Field Programmable Gate Array —
System Gates 200,000 —
Logic Elements 8,320 —
Total RAM Bits 106,496 106496
Embedded System Blocks (ESB) 52 (True Dual-Port RAM) —
Maximum User I/O 376 —
封装 484-FBGA (FineLine BGA), 23x23 mm, 1.0 mm pitch —
Core Voltage 1.8 V —
Supply Voltage Range 1.71 V to 1.89 V —
Process Technology 0.22 µm CMOS —
Logic Family CMOS —
Propagation Delay (typ.) 2.5 ns —
工作温度 0 °C to +85 °C (Commercial) 0C to +85C (commercial, [DATA_NEEDED: full Tjj range])
Configuration Modes Passive Serial, Passive Parallel Async, JTAG —
PLLs 4 —
Speed Grade -2 -1 (slowest commercial grade)
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
安装类型 Surface Mount (BGA) Surface Mount
Lead-Free [DATA_NEEDED: lead-free status] [DATA_NEEDED: lead-free status]
Product Family — APEX-20K
Series — EP20K200
Logic Elements / Cells — 8320
Number of I/O — 382
Number of Logic Gates — 200000
Package Type — 484-BBGA (Fine-pitch Ball Grid Array)
Package Suffix — BC484
Configuration Method — SRAM - external serial/parallel PROM
JTAG Support — IEEE 1149.1 boundary-scan
PLL — ClockLock / ClockBoost
Embedded Memory Blocks — Embedded System Blocks (ESBs) - RAM/ROM/CAM
MSL 等级 — [DATA_NEEDED: MSL level]

数据手册与资源

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