EP20K30EFC144-1N vs EP20K30EFC144-2X 对比
详细并排对比 EP20K30EFC144-1N 出自 Intel 和 EP20K30EFC144-2X 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP20K30EFC144-1N | EP20K30EFC144-2X |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $125.00 | $58.50 |
| Series | APEX-20KE | — |
| Device Family | APEX-20K MultiCore (LUT + Product-Term + ESB) | Altera APEX 20K |
| Gates | 30,000 | — |
| Logic Elements | 1,200 | — |
| Embedded SRAM Bits | 24,576 | — |
| User I/Os | 93 (per Mouser/Kynix listing); 408 (per alternate datasheet listing - see note) | — |
| Package Type | 144-pin FineLine BGA (FBGA) | — |
| Internal Frequency (max) | 160 MHz | — |
| Propagation Delay | 1.68 ns | — |
| Logic Family | CMOS | — |
| Core Technology | 0.22 µm CMOS, SRAM-based configuration | — |
| Supply Voltage (Core) | 1.71 V to 1.89 V (1.8 V nominal) | — |
| 工作温度 | 0 °C to 85 °C (commercial, N suffix) | — |
| Configuration Interface | IEEE 1149.1 JTAG + serial configuration (external EPCx required) | — |
| 安装类型 | Surface Mount | Surface Mount |
| RoHS 状态 | Unknown - not stated in verified sources | unknown |
| Device Type | — | Loadable programmable logic device (FPGA/CPLD hybrid) |
| Typical Gates | — | 30,000 gates |
| Number of Logic Elements / Cells | — | 1,200 cells (third-party parametric listing) |
| Number of Macrocells | — | 192 |
| Number of User I/O | — | 93 |
| Number of Terminals | — | 144 |
| Terminal Form | — | Ball |
| Package Code | — | LBGA / 144-FBGA |
| Package Shape | — | Square |
| Core Supply Voltage | — | 1.8 V |
| Process Technology | — | 0.22 um |
| Speed Grade | — | -2X |
| 工作温度范围 | — | [DATA_NEEDED: exact operating temperature range] |
| Embedded RAM Bits | — | [DATA_NEEDED: embedded memory size] |
| Supported I/O Standards | — | [DATA_NEEDED: supported I/O standards] |
| Configuration Schemes | — | [DATA_NEEDED: supported configuration schemes] |