EP20K30EFC144-2X vs EP20K30ETC144-3N 对比

详细并排对比 EP20K30EFC144-2X 出自 Altera 和 EP20K30ETC144-3N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EP20K30EFC144-2X EP20K30EFC144-2X - 30K Gate APEX 20K FPGA | Altera

EP20K30EFC144-2X - 30K Gate APEX 20K FPGA | Altera

EP20K30EFC144-2X Obsolete
Altera
EP20K30ETC144-3N EP20K30ETC144-3N - 30K Gates APEX-20KE FPGA, 144-TQFP | Altera/Intel

EP20K30ETC144-3N - 30K Gates APEX-20KE FPGA, 144-TQFP | Altera/Intel

EP20K30ETC144-3N ⚠ 最后一次采购

规格对比

参数 EP20K30EFC144-2X EP20K30ETC144-3N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $58.50 $21.50
Device Family Altera APEX 20K —
Device Type Loadable programmable logic device (FPGA/CPLD hybrid) —
Typical Gates 30,000 gates —
Number of Logic Elements / Cells 1,200 cells (third-party parametric listing) —
Number of Macrocells 192 —
Number of User I/O 93 —
Number of Terminals 144 —
Terminal Form Ball —
Package Code LBGA / 144-FBGA —
Package Shape Square —
Core Supply Voltage 1.8 V —
Process Technology 0.22 um 0.22 µm CMOS
Speed Grade -2X —
安装类型 Surface Mount Surface Mount (gull-wing)
工作温度范围 [DATA_NEEDED: exact operating temperature range] —
Embedded RAM Bits [DATA_NEEDED: embedded memory size] 24576
Supported I/O Standards [DATA_NEEDED: supported I/O standards] —
Configuration Schemes [DATA_NEEDED: supported configuration schemes] —
RoHS 状态 unknown Compliant (per legacy Altera declaration)
Family — APEX-20KE
Series — APEX 20K
Logic Elements — 1200
System Gates — 30000
Macrocells — 192
User I/Os — 92
封装 — 144-pin TQFP (TQFP-144 / ETQFP144)
Core Voltage — 1.8 V
I/O Voltage Support — 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O)
Propagation Delay (pin-to-pin) — 1.68 ns (speed grade -3)
Internal Performance — 435 MHz (per legacy datasheet)
工作温度 — 0 °C to +85 °C (commercial, 'N' suffix)
Lead-Free — Yes

数据手册与资源

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