EP20K30EFC324-1 vs EP20K30EFC324-1X 对比

详细并排对比 EP20K30EFC324-1 出自 Altera 和 EP20K30EFC324-1X 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K30EFC324-1 EP20K30EFC324-1X
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $99.50 $3.30
Manufacturer Altera (now Intel) —
Series APEX-20K APEX 20KE
Family APEX-20KE (1.8V, LVDS) APEX-20K® (MultiCore™ architecture)
Logic Elements (typical) 30,000 (30KLE) —
Typical Gates [DATA_NEEDED: typical gate count] —
Total RAM Bits 24576 —
Maximum User I/O 128 128
Core Supply Voltage (VCCINT) 1.71 V to 1.89 V —
I/O Supply Voltage [DATA_NEEDED: VCCIO range] —
封装 324-FBGA (FineLine BGA, 19x19 mm) 324-ball FBGA (FineLine BGA), 19x19 mm
安装类型 Surface Mount Surface Mount
引脚数量 324 —
Temperature Grade Commercial (per Altera family specification) —
工作温度 0C to +85C (commercial grade per Altera family spec) —
Process Technology SRAM-based, 0.18 um 0.22 µm CMOS
Configuration Passive serial / passive parallel / JTAG —
Lead-Free / RoHS [DATA_NEEDED: RoHS compliance] —
Speed Grade -1 —
MSL 等级 [DATA_NEEDED: MSL moisture sensitivity level] —
PLLs Up to 4 (per APEX-20KE family) 4
Typical Gate Count — 30,000 gates
Logic Elements (LEs) — 1,200
Embedded Memory (RAM bits) — 24,576
Dedicated Inputs — 4
Core Supply Voltage — 1.71 V to 1.89 V (1.8 V nominal)
I/O Standard Support — LVDS, LVTTL, LVCMOS, PCI, SSTL
Logic Delay (tPD) — 1.91 ns
最大时钟频率 — 909 MHz (internal), 160 MHz (I/O per partstack summary)
Configuration Method — Passive Serial, JTAG, Fast Passive Parallel
RoHS 状态 — Compliant
Operating Temperature Grade — Commercial (0 °C to +85 °C) per package suffix interpretation; industrial on -1X grade [DATA_NEEDED: exact Tj range]

数据手册与资源

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