EP20K400BC652-3V vs EP20K400BC652-1V 对比

详细并排对比 EP20K400BC652-3V 出自 Altera 和 EP20K400BC652-1V 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400BC652-3V EP20K400BC652-1V
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $195.00 $47.95
Family APEX 20K APEX 20K
Series APEX-20K® APEX-20KC
Logic Cells / Elements 16,640 —
Gates 400,000 —
Total RAM Bits 212,992 —
User I/Os 502 —
Dedicated Inputs 4 —
Maximum Operating Frequency 167 MHz —
Propagation Delay 3.6 ns (per MicrochipUSA) —
Core Supply Voltage (VCCINT) 2.375 V to 2.625 V (nominal 2.5 V) —
I/O Supply Voltage (VCCIO) [DATA_NEEDED: banked VCCIO range] —
Process Technology 0.22 µm CMOS —
工作温度 0 °C to 85 °C (commercial) 0C to +85C (commercial)
封装 652-ball BGA, 45 x 45 mm, 1.27 mm pitch 652-BGA (FineLine, 45 x 45 mm)
安装类型 Surface Mount (BGA) Surface Mount
Speed Grade -3 (faster) -1
RoHS 状态 [DATA_NEEDED: check distributor listing] [DATA_NEEDED: RoHS compliance]
Device Sub-Family — EP20K400
System Gates — 1,052,000
Maximum Logic Elements — 212,992
Macrocells / LABs — 16640
Embedded Memory (bits) — 212,992
Maximum User I/O — 502
Clock-to-Output (Tco) — 2.5 ns
Core Voltage (VCCINT) — 1.8 V
I/O Voltage (VCCIO) — 2.5 V
Configuration — SRAM-based, JTAG IEEE 1149.1
Architecture — MultiCore (LUT + product-term + ESB)

数据手册与资源

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