EP20K400CB652C7N vs EP20K400CB652C9ES 对比

详细并排对比 EP20K400CB652C7N 出自 Intel 和 EP20K400CB652C9ES 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400CB652C7N EP20K400CB652C9ES
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $158.00 $195.00
Family APEX 20KC APEX 20KC
Device Series EP20K400 —
System Gates 400,000 —
Logic Elements / Cells 16,640 16640
User I/Os 502 —
封装 652-ball PBGA (BGA-652) —
Logic Family CMOS (SRAM-based) —
Process Technology 0.15-um all-layer copper 0.15 µm CMOS
Core Voltage (VCCINT) 1.8 V —
I/O Voltage (VCCIO) 2.5 V —
Supply Voltage (general) 2.5 V —
Pin-to-Pin Propagation Delay 1.48 ns —
Internal Propagation Delay 2.5 ns —
Maximum Operating Frequency 375.94 MHz 250 MHz
工作温度 0 C to 85 C (commercial) —
安装类型 Surface Mount Surface Mount
Architecture MultiCore (LUT + embedded memory) —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Series — APEX 20KC
Total System Gates — 400000
Embedded Memory (Bits) — 212992
Number of User I/O — 488
Number of LABs/CLBs — [DATA_NEEDED: LAB count]
Number of Logic Array Blocks — 1040
Core Voltage — 1.8 V
工作温度范围 — 0°C to +85°C (Commercial)
封装 / 外壳 — 652-BGA
MSL 等级 — 3 (168 Hours)
Packaging — Tray
Programmability Type — In-system programmable (SRAM-based)
I/O Standards Supported — LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL
JTAG (IEEE 1149.1) — Yes
PLL — Yes (4-phase)

数据手册与资源

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