EP20K400CF672C-8 vs EP20K400CF672C8ES 对比

详细并排对比 EP20K400CF672C-8 出自 Altera 和 EP20K400CF672C8ES 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400CF672C-8 EP20K400CF672C8ES
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $95.00 $158.40
Family APEX 20K APEX 20KC
Logic Elements 16,640 —
Typical Gates 400,000 —
Macros 1,664 —
Maximum User I/O 488 488 (per Globalspec) / 484 (per Microchip USA) [DATA_NEEDED: confirm canonical value]
Number of I/O Banks [DATA_NEEDED: number of I/O banks] —
Package Type PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) —
Core Voltage (VCCINT) 1.8 V nominal (1.71 V to 1.89 V) —
I/O Voltage (VCCIO) [DATA_NEEDED: VCCIO options] —
Pin-to-Pin Delay (tPD) 1.78 ns (speed grade -8) —
Speed Grade -8 —
Temperature Grade (C) Commercial, 0 °C to 85 °C —
Process Technology 0.15 µm all-layer copper CMOS 0.15 µm CMOS
Embedded Memory Type ESB (RAM / ROM / CAM) —
Configuration Interface JTAG (IEEE 1149.1), Passive Serial, Passive Parallel —
JTAG Support Yes (IEEE 1149.1 boundary-scan) —
安装类型 Surface Mount (BGA) —
RoHS 状态 [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: not stated in verified data]
MSL 等级 [DATA_NEEDED: MSL level] —
Series — EP20K400
Logic Cells / Macros — 16,640
System Gates (typical) — 400,000
System Gates (maximum) — 212,992 [DATA_NEEDED: confirm datasheet interpretation]
Bidirectional I/O — 484
Propagation Delay — 2.5 ns
Maximum Internal Frequency — 301.21 MHz
Nominal Supply Voltage — 1.8 V
Supply Voltage Range — 1.71 V to 1.89 V
工作温度 — 0°C to 85°C (Commercial)
封装 — 672-BGA FineLine (FC-FBGA / S-PBGA-B672)
Logic Family — CMOS
Architecture — MultiCore™ (LUT + Embedded System Block)
Programming Method — JTAG / in-system via configuration memory

数据手册与资源

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