EP20K400CFC672-9 vs EP20K400FC672-1XGZ 对比

详细并排对比 EP20K400CFC672-9 出自 Altera 和 EP20K400FC672-1XGZ 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400CFC672-9 EP20K400FC672-1XGZ
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $325.00 $195.00
Family APEX-20KC APEX-20KE
Logic Elements / Macrocells 1664 —
Typical Gate Count 400,000 gates —
Embedded Memory (ESB) 212,992 bits —
User I/O Count 488 —
PLLs 4 —
Core Supply Voltage 1.71 V to 1.89 V 2.5 V
I/O Supply Voltage 1.5 V / 1.8 V / 2.5 V / 3.3 V —
Operating Temperature (TJ) 0 °C to 85 °C —
Speed Grade -9 (commercial, slowest bin) -1 (slowest commercial bin)
封装 672-ball FineLine BGA (FCBGA) 672-pin FBGA (Fine-pitch BGA)
Package Body Size 27 mm × 27 mm —
安装类型 Surface Mount (BGA) Surface Mount
Configuration Method EPC serial device or JTAG JTAG / passive serial / passive parallel (per APEX-20KE handbook)
Process Node [DATA_NEEDED: process node] —
RoHS 状态 [DATA_NEEDED: RoHS status] Unknown (legacy part, pre-dates widespread RoHS conversion)
Logic Elements / Cells — 16,640
System Gates — 400,000 (typical)
Embedded Memory Bits — 212,992
Maximum User I/O — 502
工作温度 — 0C to +85C (commercial)
Propagation Delay — 2.5 ns (per DigiChip listing)
Logic Family / Process — CMOS
MSL 等级 — [DATA_NEEDED: MSL level per JEDEC J-STD-020]
I/O Standards Supported — LVTTL, LVCMOS, PCI, GTL+ (per APEX-20KE family datasheet)

数据手册与资源

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