EP20K400FC672-1XGZ vs EP20K400FI672-2 对比

详细并排对比 EP20K400FC672-1XGZ 出自 Intel 和 EP20K400FI672-2 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400FC672-1XGZ EP20K400FI672-2
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $195.00 $92.40
Family APEX-20KE APEX-20K
Logic Elements / Cells 16,640 —
System Gates 400,000 (typical) —
Embedded Memory Bits 212,992 212992
Maximum User I/O 502 —
封装 672-pin FBGA (Fine-pitch BGA) —
工作温度 0C to +85C (commercial) 0 °C to +85 °C (Commercial)
Core Supply Voltage 2.5 V 2.5 V
Propagation Delay 2.5 ns (per DigiChip listing) 2.5 ns
Logic Family / Process CMOS —
Speed Grade -1 (slowest commercial bin) —
安装类型 Surface Mount Surface Mount (BGA)
MSL 等级 [DATA_NEEDED: MSL level per JEDEC J-STD-020] —
RoHS 状态 Unknown (legacy part, pre-dates widespread RoHS conversion) Lead-free / RoHS Compliant
Configuration Method JTAG / passive serial / passive parallel (per APEX-20KE handbook) —
I/O Standards Supported LVTTL, LVCMOS, PCI, GTL+ (per APEX-20KE family datasheet) —
Logic Elements — 16640
Maximum Gates — 400,000 gates
User I/Os — 502
Number of Macros — 1664
Process Technology — 0.22 µm CMOS
Maximum Internal Frequency — 200 MHz
Package Type — 672-pin Fine-pitch Ball Grid Array (FBGA/FCBGA)
PLLs (Phase-Locked Loops) — 4
Configuration Modes — JTAG, Passive Serial, Passive Parallel

数据手册与资源

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