EP20K400FI672-1N vs EP20K400FI672-2N 对比

详细并排对比 EP20K400FI672-1N 出自 Intel 和 EP20K400FI672-2N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400FI672-1N EP20K400FI672-2N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $171.00 $188.75
Family APEX 20K APEX 20K
Device EP20K400 —
Maximum System Gates 1,052,032 —
Typical Gates 400,000 400,000
Logic Elements 16,640 —
Embedded System Blocks (ESBs) 104 —
Maximum RAM Bits 212,992 —
PLLs 4 —
User I/O Pins 502 —
Total Terminals 672 —
封装 FineLine BGA-672 (26x26 mm) 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA)
Speed Grade -1 (fastest) -2
Core Voltage 2.5 V (2.375 V to 2.625 V) 2.5 V
工作温度 -40C to +85C (industrial) Commercial (0 °C to +70 °C) [DATA_NEEDED: industrial variant]
安装类型 Surface Mount Surface Mount
MSL 等级 3 —
Peak Reflow Temperature 220 C 220 °C
RoHS 状态 Compliant (Pb-free, N suffix) Compliant (lead-free)
Logic Elements / Cells — 16,640
Maximum User I/O — 488
Embedded Memory Bits — 212,992 bits
Embedded Array Blocks (EABs) — [DATA_NEEDED: EAB count per family datasheet]
Process Technology — 0.22 µm CMOS
Maximum Frequency — 200 MHz
Package Body Size — 27 x 27 mm
Terminal Pitch — 1.0 mm
Propagation Delay — 3.1 ns
湿敏等级(MSL) — 3
Configuration Modes — PS, PPS, PPA, JTAG
Supported I/O Standards — LVTTL, LVCMOS, SSTL, HSTL

数据手册与资源

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