EP20K400FI672-2 vs EP20K400FC672-1XGZ 对比

详细并排对比 EP20K400FI672-2 出自 Altera 和 EP20K400FC672-1XGZ 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400FI672-2 EP20K400FC672-1XGZ
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $92.40 $195.00
Family APEX-20K APEX-20KE
Logic Elements 16640 —
Maximum Gates 400,000 gates —
User I/Os 502 —
Embedded Memory Bits 212992 212,992
Number of Macros 1664 —
Process Technology 0.22 µm CMOS —
Core Supply Voltage 2.5 V 2.5 V
Maximum Internal Frequency 200 MHz —
Propagation Delay 2.5 ns 2.5 ns (per DigiChip listing)
工作温度 0 °C to +85 °C (Commercial) 0C to +85C (commercial)
Package Type 672-pin Fine-pitch Ball Grid Array (FBGA/FCBGA) —
PLLs (Phase-Locked Loops) 4 —
Configuration Modes JTAG, Passive Serial, Passive Parallel —
RoHS 状态 Lead-free / RoHS Compliant Unknown (legacy part, pre-dates widespread RoHS conversion)
安装类型 Surface Mount (BGA) Surface Mount
Logic Elements / Cells — 16,640
System Gates — 400,000 (typical)
Maximum User I/O — 502
封装 — 672-pin FBGA (Fine-pitch BGA)
Logic Family / Process — CMOS
Speed Grade — -1 (slowest commercial bin)
MSL 等级 — [DATA_NEEDED: MSL level per JEDEC J-STD-020]
Configuration Method — JTAG / passive serial / passive parallel (per APEX-20KE handbook)
I/O Standards Supported — LVTTL, LVCMOS, PCI, GTL+ (per APEX-20KE family datasheet)

数据手册与资源

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