EP20K400FI672-2N vs EP20K400FI672-3N 对比
详细并排对比 EP20K400FI672-2N 出自 Altera 和 EP20K400FI672-3N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP20K400FI672-2N | EP20K400FI672-3N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Unknown |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $188.75 | $0.00 |
| Family | APEX 20K | — |
| Typical Gates | 400,000 | — |
| Logic Elements / Cells | 16,640 | — |
| Maximum User I/O | 488 | — |
| Embedded Memory Bits | 212,992 bits | — |
| Embedded Array Blocks (EABs) | [DATA_NEEDED: EAB count per family datasheet] | — |
| Process Technology | 0.22 µm CMOS | CMOS |
| Core Voltage | 2.5 V | — |
| Maximum Frequency | 200 MHz | — |
| 封装 | 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA) | S-PBGA-B672 |
| Package Body Size | 27 x 27 mm | — |
| Terminal Pitch | 1.0 mm | 1.000 mm |
| Propagation Delay | 3.1 ns | 3.6 ns |
| Speed Grade | -2 | — |
| 工作温度 | Commercial (0 °C to +70 °C) [DATA_NEEDED: industrial variant] | [DATA_NEEDED: operating temperature range] |
| 湿敏等级（MSL） | 3 | — |
| Peak Reflow Temperature | 220 °C | — |
| 安装类型 | Surface Mount | Surface mount |
| RoHS 状态 | Compliant (lead-free) | unknown |
| Configuration Modes | PS, PPS, PPA, JTAG | — |
| Supported I/O Standards | LVTTL, LVCMOS, SSTL, HSTL | — |
| Device Type | — | CMOS loadable programmable logic device |
| Product Family | — | APEX 20K |
| Series | — | EP20K400 |
| 最大时钟频率 | — | 833 MHz |
| User I/O Count | — | 502 |
| Nominal Supply Voltage | — | 2.5 V |
| Supply Voltage Range | — | 2.375 V to 2.625 V |
| Terminal Count | — | 672 terminals |
| Logic Capacity | — | [DATA_NEEDED: logic capacity] |
| Configuration Method | — | [DATA_NEEDED: configuration method] |
| I/O Standard Support | — | [DATA_NEEDED: supported I/O standards] |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | unknown |