EP20K400FI672-2V vs EP20K400FI672-2N 对比

详细并排对比 EP20K400FI672-2V 出自 Intel 和 EP20K400FI672-2N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400FI672-2V EP20K400FI672-2N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $195.00 $188.75
Family APEX 20K APEX 20K
Device EP20K400 —
Logic Elements / Cells 16640 16,640
Total System Gates 400000 —
Embedded Memory Bits 212992 212,992 bits
Number of I/O 502 —
封装 672-BBGA, FCBGA 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA)
Pin / Ball Count 672 —
电源电压 2.5 V —
Process Technology 0.22 µm CMOS 0.22 µm CMOS
Propagation Delay 2.5 ns 3.1 ns
Internal Operating Frequency 200 MHz —
工作温度 0 °C to +85 °C Commercial (0 °C to +70 °C) [DATA_NEEDED: industrial variant]
Logic Family CMOS —
安装类型 Surface Mount (BGA) Surface Mount
Configuration Mode Serial / Parallel / JTAG —
RoHS 状态 [DATA_NEEDED: rohs] Compliant (lead-free)
MSL 等级 [DATA_NEEDED: msl] —
Typical Gates — 400,000
Maximum User I/O — 488
Embedded Array Blocks (EABs) — [DATA_NEEDED: EAB count per family datasheet]
Core Voltage — 2.5 V
Maximum Frequency — 200 MHz
Package Body Size — 27 x 27 mm
Terminal Pitch — 1.0 mm
Speed Grade — -2
湿敏等级(MSL) — 3
Peak Reflow Temperature — 220 °C
Configuration Modes — PS, PPS, PPA, JTAG
Supported I/O Standards — LVTTL, LVCMOS, SSTL, HSTL

数据手册与资源

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