EP20K400GC655-2N vs EP20K400GC655-1V 对比

详细并排对比 EP20K400GC655-2N 出自 Altera 和 EP20K400GC655-1V 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400GC655-2N EP20K400GC655-1V
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $127.50 $555.00
Family APEX 20KC APEX 20KE
Number of Logic Elements 16640 —
Number of Logic Cells 16640 —
Total System Gates 400000 —
Total RAM Bits 212992 —
Number of I/O [DATA_NEEDED: I/O count] —
Number of LABs/CLBs [DATA_NEEDED: LAB count] —
Core Voltage (VCCINT) 1.71 V to 1.89 V —
I/O Voltage (VCCIO) 2.5 V (LVDS-capable) —
Process Technology 0.22 µm CMOS 0.22 µm CMOS
Maximum Operating Frequency 200 MHz —
Propagation Delay (Tpd) 3.1 ns —
封装 / 外壳 655-BCPGA (Ceramic Pin Grid Array) —
Supplier Device Package 655-CPGA, 62.48 x 62.48 mm —
工作温度 Industrial (per Altera part-number -N suffix) —
安装类型 Through-Hole (CPGA, socket-compatible) —
LVDS Support Yes Yes
Architecture MultiCore (LUT + product-term + embedded memory) —
Configuration Method JTAG / Passive Serial —
RoHS 状态 [DATA_NEEDED: RoHS status] —
MSL 等级 [DATA_NEEDED: MSL level] —
Logic Elements — 16,640
Typical Gate Count — 400,000 gates
Embedded Memory — 212,992 bits
Maximum User I/O — 496
Dedicated Inputs — 6
封装 — CBGA-655 (Ceramic Ball Grid Array)
Total Terminals — 655
Supply Voltage (Core) — 2.375 V to 2.625 V (nominal 2.5 V)
Propagation Delay — 2.5 ns
Maximum Internal Frequency — 250 MHz (-1V speed grade)
Moisture Sensitivity Level — MSL 1
Peak Reflow Temperature — 220 °C
Qualification — Not Qualified
Programming Interface — IEEE 1532 / JTAG

数据手册与资源

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