EP20K400GC655-3X vs EP20K400GC655-2V 对比

详细并排对比 EP20K400GC655-3X 出自 Altera 和 EP20K400GC655-2V 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EP20K400GC655-2V EP20K400GC655-2V - 400K Gate APEX-20KC FPGA 655-CPGA | Altera

EP20K400GC655-2V - 400K Gate APEX-20KC FPGA 655-CPGA | Altera

EP20K400GC655-2V ⚠ 最后一次采购

规格对比

参数 EP20K400GC655-3X EP20K400GC655-2V
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $65.00 $92.75
Series APEX-20KC APEX-20KC
Family APEX 20K (MultiCore architecture, LUT + product-term + embedded memory) APEX 20KC (1.8 V, LVDS)
Manufacturer Altera (now Intel FPGA) —
Logic Elements / Cells 16,640 —
System Gates 400,000 ~400,000 (typical marketing figure)
Total RAM Bits 212,992 bits 212,992
Maximum Internal Frequency 167 MHz (speed grade -3) —
Process Technology 0.22 µm CMOS CMOS, 0.18 um
Core Supply Voltage (VCCINT) 1.71 V to 1.89 V —
I/O Supply Voltage (VCCIO) 2.5 V (LVDS support per APEX 20KE datasheet) —
封装 / 外壳 655-BCPGA (CPGA655, 62.48 x 62.48 mm) —
安装类型 Through-Hole (CPGA, ceramic) Through-hole (CPGA)
工作温度 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: temperature grade]
Speed Grade -3 (fastest) -2
Suffix Code -X (extended / ceramic CPGA variant) —
I/O Count [DATA_NEEDED: max user I/O] —
JTAG / Boundary Scan IEEE 1149.1 (per APEX 20K family) —
RoHS 状态 [DATA_NEEDED: RoHS status - ceramic CPGA historically non-RoHS] unknown
Logic Elements — 16,640
Number of I/O — [DATA_NEEDED: I/O count]
Core Voltage (VCCINT) — 2.375 V to 2.625 V (nominal 2.5 V)
Propagation Delay — 3.000 ns
LVDS Support — Yes
封装 — 655-CPGA (62.48 x 62.48 mm)
Package Type — Ceramic Pin Grid Array, through-hole
Lead-Free — unknown
Architecture — MultiCore (LUT + product-term + embedded memory)

数据手册与资源

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