EP20K400GI655-2V vs EP20K400GI655-1 对比
详细并排对比 EP20K400GI655-2V 出自 Intel 和 EP20K400GI655-1 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP20K400GI655-2V | EP20K400GI655-1 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $199.50 | $195.00 |
| Family | APEX 20K | APEX 20K |
| Maximum Gates | 400,000 | — |
| Logic Elements | 16,640 | 16640 |
| Embedded RAM Bits | 212,992 | — |
| User I/O Pins | 496 | — |
| Dedicated Inputs | 6 | 4 |
| 封装 | SPGA-655 (ceramic, 47 x 47 mm) | — |
| Package Equivalence Code | SPGA655,47X47 | — |
| Process Technology | 0.18 µm CMOS | — |
| Core Supply Voltage | 2.5 V (2.375 V to 2.625 V) | — |
| I/O Supply Voltage | 3.3 V | — |
| Propagation Delay | 3.0 ns to 3.1 ns | 2.5 ns |
| 湿敏等级（MSL） | 1 | — |
| Package Body Material | Ceramic | — |
| 工作温度 | Industrial (per -2V speed grade) | -40C to +85C (Industrial) |
| RoHS 状态 | Non-compliant (ceramic SPGA, contains lead) | Compliant |
| Device Series | — | EP20K400 |
| Technology | — | CMOS, SRAM-based |
| Typical Gates | — | 400000 |
| Maximum User I/O | — | 502 |
| Total Terminals | — | 655 |
| Package Type | — | Ceramic Pin Grid Array (CPGA-655) |
| JESD-30 Package Code | — | S-CPGA-P655 |
| Moisture Sensitivity Level | — | MSL 1 |
| Peak Reflow Temperature | — | 220 C |
| Programmability | — | In-system, JTAG boundary-scan (IEEE 1149.1) |
| Process Node | — | 0.18 micrometer CMOS |