EP20K400GI655-2V vs EP20K400GI655-3 对比

详细并排对比 EP20K400GI655-2V 出自 Intel 和 EP20K400GI655-3 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400GI655-2V EP20K400GI655-3
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $199.50 $55.00
Family APEX 20K APEX 20KE
Maximum Gates 400,000 —
Logic Elements 16,640 —
Embedded RAM Bits 212,992 —
User I/O Pins 496 —
Dedicated Inputs 6 4
封装 SPGA-655 (ceramic, 47 x 47 mm) 655-Pin PGA (Plastic/CPGA, square)
Package Equivalence Code SPGA655,47X47 —
Process Technology 0.18 µm CMOS CMOS, 2.5V core
Core Supply Voltage 2.5 V (2.375 V to 2.625 V) 2.5 V
I/O Supply Voltage 3.3 V 2.5 V or 3.3 V (MultiVolt I/O)
Propagation Delay 3.0 ns to 3.1 ns —
湿敏等级(MSL) 1 —
Package Body Material Ceramic —
工作温度 Industrial (per -2V speed grade) 0°C to 70°C (Industrial I grade)
RoHS 状态 Non-compliant (ceramic SPGA, contains lead) [DATA_NEEDED: RoHS status]
Logic Elements / Cells — 16,640
System Gates — 400,000 (maximum)
Maximum User I/O — 502
Number of Terminals — 655
JESD-30 Code — S-CPGA-P655
Package Shape — Square
Form of Terminal — PIN/PEG (through-hole)
安装类型 — Through-Hole (Socket)
Speed Grade — -3 (slowest of the EP20K400 family)
Configuration Modes — Passive Serial, Passive Parallel Asynchronous, JTAG
Embedded Memory — Dual-port RAM via Embedded System Blocks (ESBs)
JTAG / Boundary Scan — IEEE 1149.1 compliant

数据手册与资源

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