EP20K400GI655-3V vs EP20K400GC655-3V 对比
详细并排对比 EP20K400GI655-3V 出自 Intel 和 EP20K400GC655-3V 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Intel
EP20K400GI655-3V - APEX 20K 400K-Gate FPGA, 16K LE, 655-Pin PGA | Altera (Intel)
EP20K400GI655-3V Obsolete规格对比
| 参数 | EP20K400GI655-3V | EP20K400GC655-3V |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $142.50 | $160.00 |
| Series | APEX 20K | APEX-20KC |
| Device Family | EP20K400 | — |
| Logic Elements | 16,640 | 16640 |
| Typical Gate Count | 400,000 gates | 400000 |
| Maximum User I/O | 496 | — |
| Dedicated Inputs | 6 | — |
| Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | — |
| Total Embedded RAM | [DATA_NEEDED: total RAM bits] | — |
| Technology | CMOS (0.18 µm process) | — |
| Maximum Internal Clock Frequency | 714.2 MHz | — |
| Supply Voltage VCCINT | 2.5 V | — |
| I/O Supply Voltage VCCIO | 2.5 V or 3.3 V | — |
| 封装 | 655-pin SPGA (Staggered PGA), 47 x 47 mm | 655-BCPGA (62.48 mm x 62.48 mm) |
| 安装类型 | Through-Hole (Pin Grid Array) | Through Hole (CPGA) |
| 工作温度 | -40 °C to +85 °C (industrial) | [DATA_NEEDED: commercial / industrial / military grade] |
| 湿敏等级（MSL） | 1 | — |
| Qualification | Not Qualified | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance flag - BCPGA package often non-RoHS] |
| Configuration Interface | IEEE 1149.1 JTAG + serial / parallel passive | — |
| Family | — | APEX 20KC (Apex 20KE Device Family, 1.8 V, LVDS) |
| Manufacturer | — | Altera (now Intel) |
| Core Supply Voltage | — | 1.71 V to 1.89 V (1.8 V nominal) |
| Total RAM Bits | — | 212992 |
| Number of User I/O | — | 496 |
| 最大时钟频率 | — | 714.2 MHz |
| Propagation Delay | — | 3.6 ns |
| Speed Grade | — | -3V (commercial temperature, Vcc 1.8 V) |
| Package Equivalence Code | — | SPGA655, 47x47 |
| Peak Reflow Temperature | — | 220 C |
| Process Technology | — | CMOS |
| Configuration | — | SRAM-based (requires EPC configuration device) |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |