EP20K600CB652C8N vs EP20K600CB652C9N 对比

详细并排对比 EP20K600CB652C8N 出自 Altera 和 EP20K600CB652C9N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K600CB652C8N EP20K600CB652C9N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $115.00 $128.00
Family APEX 20KC APEX 20KC
Device Type Loadable PLD / FPGA Loadable PLD (FPGA)
System Gates 600,000 —
Logic Elements 24,320 cells 24,320
Embedded Memory 311,296 bits —
User I/O Pins 488 —
Dedicated Inputs 4 —
Outputs 480 —
Propagation Delay (typ.) 1.48 ns —
Pin-to-Pin Timing 1.78 ns —
Internal Frequency (typ.) 301.21 MHz —
Core Supply Voltage 1.8 V nominal (1.71 V to 1.89 V) 1.8 V
Process Technology 0.18 µm all-layer copper-metal 0.15 micron all-layer copper CMOS
Speed Grade C8 C9 (~1.48 ns propagation delay)
工作温度 0 °C to 85 °C (commercial) 0 C to 85 C (commercial)
封装 652-ball LBGA, 45 x 45 mm, 1.27 mm pitch BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch)
安装类型 Surface Mount (BGA) Surface Mount (BGA)
Architecture MultiCore LUT + Embedded System Blocks (ESB) MultiCore LUT + embedded system memory (ESB)
Pin-Compatible With APEX 20KE family —
RoHS 状态 unknown [DATA_NEEDED: rohs status]
Typical Gates — 600,000
Maximum User I/O — 488
On-chip Memory — Embedded system memory blocks (dual-port RAM, FIFO)
Configuration Interface — JTAG (IEEE 1149.1) and serial/PROM configuration
Pin/Pin Compatibility — Pin-compatible with APEX 20KE devices of same package
Toolchain — Altera/Intel Quartus II (legacy APEX support)
MSL 等级 — [DATA_NEEDED: MSL level]

数据手册与资源

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