EP20K600CB652C9N vs EP20K600CB652C-8 对比

详细并排对比 EP20K600CB652C9N 出自 Intel 和 EP20K600CB652C-8 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K600CB652C9N EP20K600CB652C-8
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $128.00 $86.00
Family APEX 20KC APEX 20KC (MultiCore)
Device Type Loadable PLD (FPGA) —
Typical Gates 600,000 600,000
Logic Elements 24,320 24,320
Maximum User I/O 488 —
封装 BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch) 652-BGA (LBGA, 45 x 45 mm, 1.27 mm pitch)
Process Technology 0.15 micron all-layer copper CMOS —
Core Supply Voltage 1.8 V —
Speed Grade C9 (~1.48 ns propagation delay) -8 (slowest, most timing margin)
Architecture MultiCore LUT + embedded system memory (ESB) —
On-chip Memory Embedded system memory blocks (dual-port RAM, FIFO) —
Configuration Interface JTAG (IEEE 1149.1) and serial/PROM configuration —
工作温度 0 C to 85 C (commercial) 0 C to 85 C (commercial)
安装类型 Surface Mount (BGA) Surface Mount (thermally enhanced)
Pin/Pin Compatibility Pin-compatible with APEX 20KE devices of same package —
Toolchain Altera/Intel Quartus II (legacy APEX support) —
RoHS 状态 [DATA_NEEDED: rohs status] —
MSL 等级 [DATA_NEEDED: MSL level] —
Series — APEX 20KC
Embedded RAM — 311,296 bits
User I/Os — 488
Propagation Delay — 1.48 ns (per published source)
VCCIO Options — 1.8 V / 2.5 V / 3.3 V
Process — 0.15 µm all-layer copper metal
PCI Compliance — PCI Local Bus Rev 2.2 at 33/66 MHz, 32/64-bit
Memory Interface Support — DDR SDRAM, ZBT SRAM, QDR SRAM, LVDS
Configuration — Enhanced (EPC) bitstream

数据手册与资源

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