EP20K600CEF672C7 vs EP20K600CF672C-7ES 对比

详细并排对比 EP20K600CEF672C7 出自 Intel 和 EP20K600CF672C-7ES 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K600CEF672C7 EP20K600CF672C-7ES
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $98.40 $2,050.00
Manufacturer Intel (formerly Altera) —
Series APEX 20KC —
Family APEX 20KC (Enhanced Configuration) APEX 20KC
Device Type FPGA / Loadable PLD Field Programmable Gate Array (FPGA)
Logic Elements / Cells 24,320 —
Gate Count (typical) 600,000 gates —
Maximum Operating Frequency 375.94 MHz —
Propagation Delay 1.48 ns (typ) 1.48 ns to 1.6 ns
User I/Os 488 —
Core Supply Voltage 1.8 V —
Process Technology 0.15 µm CMOS, all-layer copper 0.15 micron all-layer copper CMOS
封装 672-ball FineLine BGA (FC-FBGA) 672-ball FCBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch
Package Code BGA-652, 45 x 45 mm, 1.27 mm pitch —
工作温度 0 °C to +85 °C (commercial) 0 C to 85 C (Commercial)
Configuration SRAM-based, serial or parallel (EPC) —
Embedded Memory EAB blocks (dual-port RAM with byte enables) —
LVDS Support True-LVDS channels integrated —
MultiVolt I/O 1.8 V, 2.5 V, 3.3 V interfaces —
External Memory Interface DDR SDRAM, QDR SRAM —
JTAG Support IEEE 1149.1 boundary-scan —
RoHS 状态 [DATA_NEEDED: RoHS status] —
Maximum System Gates — 1,560,000 (typical 600K application gates)
Typical Logic Elements — 24,320 (per APEX 20KC 600K family)
Maximum User I/O — 488
Total I/O Lines — 504 (per Microchip USA listing)
Total Inputs — 508
Embedded System Blocks (ESBs) — 248
Embedded RAM — 248 Kbits (dual-port)
PLLs — 4
最大时钟频率 — 1666.6 MHz
Speed Grade — -7
Core Voltage — 1.8 V (typical APEX 20KC, exact value per datasheet)
Configuration Mode — EPC serial / JTAG IEEE 1149.1
Compliance — RoHS status unknown (verify with manufacturer datasheet)

数据手册与资源

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