EP20K600CF672C-7ES vs EP20K400CF672C7ES 对比

详细并排对比 EP20K600CF672C-7ES 出自 Altera 和 EP20K400CF672C7ES 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K600CF672C-7ES EP20K400CF672C7ES
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $2,050.00 $152.00
Family APEX 20KC APEX 20KC
Device Type Field Programmable Gate Array (FPGA) Loadable PLD / FPGA
Maximum System Gates 1,560,000 (typical 600K application gates) —
Typical Logic Elements 24,320 (per APEX 20KC 600K family) —
Maximum User I/O 488 488
Total I/O Lines 504 (per Microchip USA listing) —
Total Inputs 508 —
Embedded System Blocks (ESBs) 248 —
Embedded RAM 248 Kbits (dual-port) —
PLLs 4 —
Propagation Delay 1.48 ns to 1.6 ns 1.4 ns
最大时钟频率 1666.6 MHz —
Speed Grade -7 C7 (commercial, -7)
Process Technology 0.15 micron all-layer copper CMOS 0.18 um CMOS
封装 672-ball FCBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch —
工作温度 0 C to 85 C (Commercial) 0C to +85C (commercial)
Core Voltage 1.8 V (typical APEX 20KC, exact value per datasheet) 1.8 V
Configuration Mode EPC serial / JTAG IEEE 1149.1 —
Compliance RoHS status unknown (verify with manufacturer datasheet) —
Series — EP20K400
Logic Elements (Cells) — 16,640
System Gates — 400,000
Embedded Memory (Bits) — 212,992
Total RAM Bits — 212,992
I/O Lines — 484
Input Lines — 488
Number of PLLs — 4
Maximum Internal Clock Frequency — 375.94 MHz
MultiVolt I/O — 1.5 V / 1.8 V / 2.5 V / 3.3 V
Package Type — 672-ball FineLine BGA
Package Code — FC-FBGA-B672
Ball Pitch — 1.000 mm
安装类型 — Surface Mount
RoHS 状态 — [DATA_NEEDED: RoHS compliance]

数据手册与资源

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