EP20K600CF672C-9 vs EP20K600CF672C-7ES 对比

详细并排对比 EP20K600CF672C-9 出自 Altera 和 EP20K600CF672C-7ES 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K600CF672C-9 EP20K600CF672C-7ES
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $171.00 $2,050.00
Device Type FPGA (APEX 20KC family, complex PLD) Field Programmable Gate Array (FPGA)
Typical Gate Count 600,000 gates —
Logic Elements (LEs) [DATA_NEEDED: logic element count] —
Embedded System Blocks (ESBs) [DATA_NEEDED: ESB count and total RAM bits] 248
User I/Os 488 pins —
PLLs 4 4
封装 672-ball FBGA (45 x 45 mm, 1.27 mm pitch) 672-ball FCBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch
引脚数量 672 —
Core Supply Voltage (VCCINT) 1.8 V —
I/O Supply Voltage (VCCIO) 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) —
Propagation Delay 1.48 ns 1.48 ns to 1.6 ns
工作温度 0 °C to +85 °C (commercial) 0 C to 85 C (Commercial)
Speed Grade -9 -7
Process Technology 0.15 µm all-layer copper interconnect 0.15 micron all-layer copper CMOS
Configuration Interface Serial (EPC16 / EPC8 / EPC4 / EPC2 / EPC1) —
安装类型 Surface Mount (BGA) —
RoHS 状态 unknown —
Family — APEX 20KC
Maximum System Gates — 1,560,000 (typical 600K application gates)
Typical Logic Elements — 24,320 (per APEX 20KC 600K family)
Maximum User I/O — 488
Total I/O Lines — 504 (per Microchip USA listing)
Total Inputs — 508
Embedded RAM — 248 Kbits (dual-port)
最大时钟频率 — 1666.6 MHz
Core Voltage — 1.8 V (typical APEX 20KC, exact value per datasheet)
Configuration Mode — EPC serial / JTAG IEEE 1149.1
Compliance — RoHS status unknown (verify with manufacturer datasheet)

数据手册与资源

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