EP20K600EFC33-2X vs EP20K600EBC652-2X 对比

详细并排对比 EP20K600EFC33-2X 出自 Altera 和 EP20K600EBC652-2X 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K600EFC33-2X EP20K600EBC652-2X
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $815.00 $275.00
Series APEX-20KE —
Family APEX 20K (System-on-a-Programmable-Chip) —
Logic Elements / Cells 24320 —
Total Gates 600000 —
Total RAM Bits 311296 —
Number of I/O 588 —
Core Supply Voltage 1.71 V to 1.89 V (1.8 V nominal) 2.5 V
Process Technology 0.15 um all-layer copper metal 0.15 µm all-layer copper CMOS
Maximum Internal Frequency 200 MHz —
Propagation Delay 1.48 ns 1.48 ns
工作温度 0C to +85C 0 °C to +85 °C (commercial)
封装 1020-ball FC-FBGA (33 mm x 33 mm) 652-ball BGA, 45 x 45 mm, 1.27 mm pitch
Ball Pitch 1.27 mm —
安装类型 Surface Mount Surface Mount
RoHS 状态 Non-compliant (legacy Altera product) [DATA_NEEDED: RoHS status]
Lead-Free Status Contains lead (legacy) —
Multi-Voltage I/O Support 1.5V / 1.8V / 2.5V / 3.3V / 5.0V —
Embedded System Blocks Dual-port RAM / FIFO configurable —
Device Family — APEX 20KE
Device Type — SPLD / FPGA (Field Programmable Gate Array)
Logic Elements (LEs) — 24,320
Macros — 24,320
Embedded Memory Bits — 311,296 bits
User I/Os — 488
Total Pins / Balls — 652
I/O Standard Support — LVTTL, LVCMOS, PCI, SSTL, GTL+
Configuration Modes — Passive serial, passive parallel, JTAG (IEEE 1149.1)

数据手册与资源

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