EP20K60EFC144-1 vs EP20K30EFC144-2X 对比
详细并排对比 EP20K60EFC144-1 出自 Altera 和 EP20K30EFC144-2X 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP20K60EFC144-1 | EP20K30EFC144-2X |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $19.40 | $58.50 |
| Device Family | APEX 20KE | Altera APEX 20K |
| Series | APEX 20K | — |
| Logic Family | CMOS | — |
| Typical Gates | 60,000 | 30,000 gates |
| Maximum System Gates | 256,000 | — |
| Macrocells | 256 | — |
| Maximum User I/Os | 93 (per datasheet; 196 max in 144-FBGA family datasheet) | — |
| Embedded Memory | 32,768 bits (2560 RAM blocks) | — |
| Maximum Internal Frequency | 160 MHz | — |
| Propagation Delay | 1.72 ns | — |
| Core Supply Voltage | 1.8 V | 1.8 V |
| Speed Grade | -1 | -2X |
| 工作温度 | 0 C to 85 C (Commercial) | — |
| 封装 | 144-FBGA (Fine-pitch BGA) | — |
| Package Pin Count | 144 balls | — |
| 安装类型 | Surface Mount | Surface Mount |
| RoHS 状态 | [DATA_NEEDED: rohs_status] | unknown |
| Programming Interface | JTAG / ByteBlaster / Altera Programming Unit | — |
| Device Type | — | Loadable programmable logic device (FPGA/CPLD hybrid) |
| Number of Logic Elements / Cells | — | 1,200 cells (third-party parametric listing) |
| Number of Macrocells | — | 192 |
| Number of User I/O | — | 93 |
| Number of Terminals | — | 144 |
| Terminal Form | — | Ball |
| Package Code | — | LBGA / 144-FBGA |
| Package Shape | — | Square |
| Process Technology | — | 0.22 um |
| 工作温度范围 | — | [DATA_NEEDED: exact operating temperature range] |
| Embedded RAM Bits | — | [DATA_NEEDED: embedded memory size] |
| Supported I/O Standards | — | [DATA_NEEDED: supported I/O standards] |
| Configuration Schemes | — | [DATA_NEEDED: supported configuration schemes] |