EP20K60EFC144-1 vs EP20K60EFI144-2X 对比

详细并排对比 EP20K60EFC144-1 出自 Altera 和 EP20K60EFI144-2X 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K60EFC144-1 EP20K60EFI144-2X
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $19.40 $65.00
Device Family APEX 20KE APEX 20KE
Series APEX 20K —
Logic Family CMOS —
Typical Gates 60,000 60,000
Maximum System Gates 256,000 —
Macrocells 256 —
Maximum User I/Os 93 (per datasheet; 196 max in 144-FBGA family datasheet) —
Embedded Memory 32,768 bits (2560 RAM blocks) —
Maximum Internal Frequency 160 MHz —
Propagation Delay 1.72 ns —
Core Supply Voltage 1.8 V —
Speed Grade -1 -2 (industrial, -2X suffix)
工作温度 0 C to 85 C (Commercial) -40 °C to +85 °C
封装 144-FBGA (Fine-pitch BGA) —
Package Pin Count 144 balls —
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS compliance status]
Programming Interface JTAG / ByteBlaster / Altera Programming Unit —
Logic Elements — 2,560
Maximum Operating Frequency — 200 MHz
Process Technology — 0.22 µm CMOS
Core Supply Voltage (VCCINT) — 1.8 V (range 1.71 V to 1.89 V)
Propagation Delay (tpd) — 2.41 ns
User I/O Pins — 93
Dedicated Inputs — 4
Total Terminals — 144
Package Type — FBGA-144 (FineLine BGA, LBGA)
Package Code — LBGA
Terminal Form — Ball
Architecture — MultiCore (LUT + product-term + embedded memory)
I/O Standard Support — LVDS, 1.8 V I/O
Configuration Interface — JTAG (IEEE 1149.1) / serial PROM / parallel PROM
湿敏等级(MSL) — 3

数据手册与资源

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