EP2A15B724C9 vs EP2A15F672C9 对比

详细并排对比 EP2A15B724C9 出自 Intel 和 EP2A15F672C9 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A15B724C9 EP2A15F672C9
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $268.50 $175.00
Series APEX II —
Family APEX II (EP2A15) —
Logic Elements 16640 16640
Number of Gates 600000 —
Embedded Memory (RAM bits) 425984 —
User I/O Count 492 —
Supply Voltage (Core) 1.5 V —
I/O Voltages Supported 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O) —
Process Technology 0.15 µm all-layer copper (up to 8 metal layers) 0.15 µm all-layer copper (up to 8 metal layers)
Maximum Internal Frequency 500 MHz 379 MHz
LVDS Data Rate Up to 1 Gbps (True-LVDS) —
Interface Standards LVDS, LVPECL, PCML, HyperTransport —
Embedded Memory Type ESB - dual-port RAM / ROM / FIFO / CAM —
Clock Management On-chip PLLs —
封装 724-ball FCBGA (Fine-pitch Chip-Scale BGA) 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine)
工作温度 Commercial (0 °C to +85 °C) 0 °C to 85 °C (commercial)
安装类型 Surface Mount —
RoHS 状态 [DATA_NEEDED: RoHS status] —
Logic Family — APEX II (CMOS)
Usable Gates — 600 K
Macrocells — 1664
Maximum User I/Os — 492
Core Supply Voltage — 1.5 V
I/O Supply Voltage — 3.3 V
Propagation Delay — 1.94 ns
High-Speed I/O Support — True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps
Embedded Memory — ESB dual-port RAM / FIFO
Configuration Interface — Passive serial / Active serial / JTAG (IEEE 1149.1)
PLLs — On-chip PLLs for clock synthesis and deskew
Compliance — RoHS - [DATA_NEEDED: status not in verified data]; IEEE 1149.1 boundary scan

数据手册与资源

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