EP2A15F672C9N vs EP2A15F672C9 对比

详细并排对比 EP2A15F672C9N 出自 Intel 和 EP2A15F672C9 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A15F672C9N EP2A15F672C9
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $155.00 $175.00
Logic Family APEX II (CMOS) APEX II (CMOS)
Series Altera APEX II (EP2A) —
Logic Elements / Cells 16,640 —
Equivalent Gates 600,000 —
Maximum User I/O Pins 492 —
Propagation Delay 1.94 ns 1.94 ns
Internal Operating Frequency (max) 379 MHz —
Technology Process 0.15 µm all-layer copper CMOS, up to 8 metal layers —
Core Supply Voltage 1.5 V 1.5 V
封装 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine BGA) 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine)
工作温度 0°C to +85°C (commercial grade) 0 °C to 85 °C (commercial)
安装类型 Surface Mount —
MSL 等级 3 (per FC-FBGA moisture sensitivity, typical) —
RoHS 状态 [DATA_NEEDED: RoHS compliance status] —
Lead-Free / Halogen-Free [DATA_NEEDED: lead-free status] —
I/O Speed Grade Up to 1 Gbps (LVDS) —
Embedded Memory Embedded dual-port RAM blocks ESB dual-port RAM / FIFO
Special Blocks CAM (Content-Addressable Memory), dedicated multipliers, PLLs —
Speed Grade C9 (fastest commercial grade in the APEX II speed-grade system) —
Usable Gates — 600 K
Logic Elements — 16640
Macrocells — 1664
Maximum User I/Os — 492
Process Technology — 0.15 µm all-layer copper (up to 8 metal layers)
I/O Supply Voltage — 3.3 V
Maximum Internal Frequency — 379 MHz
High-Speed I/O Support — True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps
Configuration Interface — Passive serial / Active serial / JTAG (IEEE 1149.1)
PLLs — On-chip PLLs for clock synthesis and deskew
Compliance — RoHS - [DATA_NEEDED: status not in verified data]; IEEE 1149.1 boundary scan

数据手册与资源

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