EP2A25B652C9 vs EP2A25B652C7 对比

详细并排对比 EP2A25B652C9 出自 Intel 和 EP2A25B652C7 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A25B652C9 EP2A25B652C7
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $105.00 $285.00
Device Family APEX II (EP2A25) —
Logic Elements 24,320 Approximately 25,000 LE
封装 652-ball FineLine BGA 652-ball FineLine BGA
Speed Grade C9 (-7 commercial) -7
Process Technology 0.18 µm CMOS —
工作温度范围 [DATA_NEEDED: commercial/industrial temperature range] —
Core Voltage (VCCINT) 1.8 V —
I/O Voltage Standards LVTTL, LVCMOS, SSTL, LVDS —
Configuration Interface JTAG (IEEE 1149.1), passive serial, MAX configuration scheme —
Embedded Memory Embedded array blocks (EABs) —
Embedded Multipliers Yes (DSP blocks) —
Maximum User I/O [DATA_NEEDED: maximum usable I/O count for 652 BGA] —
RoHS 状态 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] —
安装类型 Surface Mount (BGA) —
MSL 等级 [DATA_NEEDED: moisture sensitivity level] —
Family — APEX II
Embedded System Blocks (ESBs) — [DATA_NEEDED: ESB count]
Maximum User I/O Pins — 488
Core Voltage — 1.5 V
I/O Bank Voltage — 1.5 V / 1.8 V / 2.5 V / 3.3 V
RAM Bits (approx.) — 40,960
PLLs — 4
Supported I/O Standards — LVTTL, LVCMOS, SSTL, LVDS
Configuration Method — JTAG / Passive Serial / Active Serial
Boundary Scan — IEEE 1149.1 compliant
Design Software — Quartus II
工作温度 — Commercial 0C to +85C

数据手册与资源

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