EP2A25F672C7 vs EP2A25F672C9 对比
详细并排对比 EP2A25F672C7 出自 Altera 和 EP2A25F672C9 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2A25F672C7 | EP2A25F672C9 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $118.00 | $700.00 |
| Product Family | APEX II | — |
| Logic Elements | 25,000 | — |
| Maximum System Gates | 1,650,000 | — |
| Maximum RAM Bits | 422,976 | — |
| User I/O Count | 492 | — |
| 封装 | 672-ball FCBGA (FineLine BGA) | 672-ball FCBGA (FineLine BGA) |
| Process Technology | 0.15-um all-layer copper, up to 8 metal layers | 0.15 µm all-layer copper, up to 8 metal layers |
| Supply Voltage (Core) | 1.5 V | — |
| LVDS Data Rate | 1 Gbps per channel (True-LVDS) | — |
| I/O Standards Supported | LVDS, LVPECL, PCML, HyperTransport | — |
| 工作温度 | 0C to +85C (Commercial) | 0°C to 85°C (Commercial) |
| Speed Grade | -7 | — |
| Configuration Mode | Passive Serial, Passive Parallel, JTAG | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED] |
| Embedded System Blocks (ESB) | Yes - RAM, ROM, CAM, multiplier support | — |
| Family | — | APEX II |
| Logic Elements (LE) | — | Approximately 25,000 |
| Macro Cells | — | 2432 |
| User I/O | — | 492 |
| Package Dimensions | — | 27 mm x 27 mm |
| Ball Pitch | — | 1.0 mm |
| Logic Family | — | CMOS |
| Propagation Delay | — | 1.69 ns |
| 电源电压 | — | [DATA_NEEDED: core VCC voltage] |
| I/O Standards | — | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V) |
| Configuration | — | Passive Serial, Passive Parallel Synchronous, JTAG |
| Embedded Memory | — | ESBs for dual-port RAM, ROM, FIFO |
| 安装类型 | — | Surface Mount |