EP2A25F672C7N vs EP2A25B724C7 对比

详细并排对比 EP2A25F672C7N 出自 Altera 和 EP2A25B724C7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A25F672C7N EP2A25B724C7
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $195.00 $760.00
Family APEX II APEX II
Logic Elements 24,320 cells 24,320
System Gates Approximately 900,000 900,000
User I/Os 492 —
Propagation Delay (tPD) 1.69 ns —
Internal Operating Frequency Up to 500 MHz —
Core Voltage (VCCINT) 1.5 V —
Process Technology 0.15 µm all-layer copper (up to 8 metal layers) 0.15 µm CMOS
Logic Family CMOS —
Package Type 672-ball FC-FBGA (FineLine BGA) —
Package Body Size 27 x 27 mm —
Ball Pitch 1.0 mm —
工作温度 0 °C to 85 °C (commercial) 0 °C to +85 °C (commercial)
High-Speed I/O Support True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps —
Programmable Logic Type Loadable PLD (in-system programmable) —
Embedded Memory Embedded System Blocks (ESB) configurable as dual-port RAM/ROM —
PLLs Up to 4 8
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
Maximum User I/O — 540
Internal Frequency — 500 MHz
Speed Grade — -7
Core Supply Voltage — 1.425 V to 1.575 V (1.5 V nominal)
封装 — 724-BBGA / FCBGA (35 mm × 35 mm)
Embedded System Blocks (ESB) — Yes (dual-port RAM/ROM)
Multipliers — Yes (dedicated DSP blocks)
Configuration Interface — JTAG (IEEE 1149.1)

数据手册与资源

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