EP2A25F672C8 vs EP2A25B724C7 对比

详细并排对比 EP2A25F672C8 出自 Altera 和 EP2A25B724C7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A25F672C8 EP2A25B724C7
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $951.18 $760.00
Family APEX II (EP2A25) APEX II
Logic Elements 25,000 (typical gates) 24,320
Maximum System Gates 40,960 —
Macrocells / Embedded Logic 2,432 macros —
User I/O Count 492 —
封装 672-FBGA (FineLine BGA, 27x27 mm, 1.0 mm pitch) 724-BBGA / FCBGA (35 mm × 35 mm)
Propagation Delay (tpd) 1.69 ns —
Speed Grade C8 -7
工作温度 0 C to 85 C (commercial) 0 °C to +85 °C (commercial)
Process Technology 0.15 microm CMOS, 8-layer copper interconnect 0.15 µm CMOS
I/O Standards Supported LVTTL, LVCMOS, PCI-X, GTL+, SSTL-2/3, HSTL, LVDS, LVPECL —
LVDS Data Rate 1 Gbps —
PLL Count 4 —
Embedded Memory ESB blocks (dual-port RAM, FIFO, CAM, ROM) —
I/O Banks 16 —
安装类型 Surface Mount Surface Mount
RoHS 状态 Non-compliant (legacy product) [DATA_NEEDED: RoHS status]
System Gates — 900,000
Maximum User I/O — 540
Internal Frequency — 500 MHz
Core Supply Voltage — 1.425 V to 1.575 V (1.5 V nominal)
Embedded System Blocks (ESB) — Yes (dual-port RAM/ROM)
PLLs — 8
Multipliers — Yes (dedicated DSP blocks)
Configuration Interface — JTAG (IEEE 1149.1)

数据手册与资源

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