EP2A25F672I8 vs EP2A25F672C7 对比

详细并排对比 EP2A25F672I8 出自 Altera 和 EP2A25F672C7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A25F672I8 EP2A25F672C7
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $125.00 $118.00
Family APEX II —
Logic Elements / Cells 24,320 —
Equivalent Gates 900,000 —
Embedded Memory (RAM bits) 622,592 —
User I/Os 492 —
Number of PLLs 4 —
Process Technology 0.15 µm CMOS, up to 8 metal layers 0.15-um all-layer copper, up to 8 metal layers
Core Supply Voltage 1.5 V —
Propagation Delay 1.69 ns (typical) —
Internal Performance 333 MHz (per legacy datasheet) —
LVDS / High-Speed I/O Yes, up to 1 Gbps —
封装 672-ball FC-FBGA (FineLine BGA), 27 × 27 mm, 1 mm pitch 672-ball FCBGA (FineLine BGA)
安装类型 Surface Mount (BGA) —
工作温度 –40 °C to +85 °C (industrial, 'I' grade) 0C to +85C (Commercial)
Speed Grade I8 (industrial, 8-speed-grade per APEX II ordering scheme) -7
JTAG / Boundary Scan IEEE 1149.1 compliant —
I/O Standards Supported LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, GTL+, PCI LVDS, LVPECL, PCML, HyperTransport
RoHS 状态 unknown [DATA_NEEDED: RoHS status]
Lead-Free Status unknown —
Product Family — APEX II
Logic Elements — 25,000
Maximum System Gates — 1,650,000
Maximum RAM Bits — 422,976
User I/O Count — 492
Supply Voltage (Core) — 1.5 V
LVDS Data Rate — 1 Gbps per channel (True-LVDS)
Configuration Mode — Passive Serial, Passive Parallel, JTAG
Embedded System Blocks (ESB) — Yes - RAM, ROM, CAM, multiplier support

数据手册与资源

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