EP2A40F1020C8N vs EP2A40F1020C8 对比
详细并排对比 EP2A40F1020C8N 出自 Intel 和 EP2A40F1020C8 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2A40F1020C8N | EP2A40F1020C8 |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $0.00 | $310.00 |
| Product Type | Field-Programmable Gate Array (FPGA) | — |
| Device Family | APEX II | — |
| Logic Technology | CMOS | — |
| Logic Gates | 1.5 million | — |
| Logic Cells | 38,400 | 38,400 |
| Nominal Supply Voltage | 1.5 V | — |
| Supply Voltage Range | 1.425 V to 1.575 V | — |
| User I/Os | 735 | — |
| Package Terminal Count | 1,020 pins | — |
| Package Type | FC-FBGA, BGA-1020 | FC-FBGA (FineLine BGA) |
| Package Body Size | 33 mm x 33 mm | — |
| Ball Pitch | 1 mm | 1.0 mm |
| Reported Operating Frequency | 376 MHz | — |
| Alternative Reported Frequency | 562 MHz | — |
| Reported Propagation Delay | 1.78 ns | — |
| Alternative Reported Propagation Delay | 1.55 ns | — |
| Fabrication Process | 0.15 µm | — |
| Maximum Reported Metal Layers | 8 layers | — |
| 工作温度 | 0 °C to 85 °C | 0 C to +85 C (commercial, 'C' suffix) |
| 安装类型 | Surface Mount | — |
| Terminal Form | Ball | — |
| RoHS 状态 | unknown | [DATA_NEEDED: confirm per lot] |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Family | — | APEX II |
| Logic Family | — | CMOS |
| Process Technology | — | 0.15 µm all-layer copper, up to 8 metal layers |
| System Gates | — | 1,500,000 |
| Macros / Macro Cells | — | 2,560 |
| Embedded RAM | — | [DATA_NEEDED: total ESB bits] |
| Maximum Internal Frequency | — | 376 MHz |
| Propagation Delay | — | 1.55 ns |
| User I/O Pins | — | 735 |
| Core Voltage (VCCINT) | — | 1.5 V |
| I/O Voltage (VCCIO) | — | MultiVolt 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5.0 V |
| Package Pin Count | — | 1020 |
| Package Dimensions | — | 33 x 33 mm |
| Configuration Interface | — | JTAG / Altera serial |
| Design Toolchain | — | Quartus II (legacy version 4.x or earlier recommended) |