EP2A40F1020C9ES vs EP2A40F1020C7N 对比

详细并排对比 EP2A40F1020C9ES 出自 Altera 和 EP2A40F1020C7N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A40F1020C9ES EP2A40F1020C7N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $98.00 $198.00
Family APEX II APEX II
System Gates 1.5 M 1,500,000 (1.5 M)
Logic Cells / Elements 38,400 —
Maximum Internal Clock Frequency 366 MHz —
Process Technology 0.15 µm CMOS —
Core Supply Voltage 1.5 V 1.5 V nominal (1.425 V – 1.575 V)
封装 1020-pin FC-FBGA FC-FBGA-1020, 33 × 33 mm, 1.0 mm pitch, fine-line
Package Type Flip-Chip Fine-Pitch Ball Grid Array —
安装类型 Surface Mount Surface Mount
Embedded Memory Embedded System Blocks (ESBs) - RAM/ROM ESB-based, 504 Kbits total
I/O Standards LVDS and other high-speed standards (per family datasheet) —
RAM Support Synchronous and asynchronous —
工作温度 [DATA_NEEDED: operating temperature grade] 0 °C to +85 °C (commercial, C7 grade)
RoHS 状态 [DATA_NEEDED: RoHS status] —
Lead-Free [DATA_NEEDED: lead-free status] —
Technology — 0.15 µm all-layer copper CMOS, up to 8 metal layers
Logic Elements — 38,400
Maximum Internal Performance — 562 MHz
Propagation Delay — 1.55 ns
User I/O Pins — 735
PLLs — 4
Clock Networks — 12
True-LVDS Data Rate — 1 Gbps
Supported I/O Standards — True-LVDS, LVPECL, PCML, HyperTransport, LVTTL, LVCMOS, PCI, SSTL
Logic Family — CMOS
Terminal Form — BGA ball (flip-chip)

数据手册与资源

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