EP2A40F672C6 vs EP2A40F672C7 对比

详细并排对比 EP2A40F672C6 出自 Altera 和 EP2A40F672C7 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A40F672C6 EP2A40F672C7
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $105.00 $195.00
Family APEX II APEX II
Device EP2A40 —
Logic Elements (typical) 40,000 —
Maximum System Gates [DATA_NEEDED: maximum system gates] —
Embedded System Blocks (ESBs) [DATA_NEEDED: ESB count] —
Maximum User I/O Pins [DATA_NEEDED: max user I/O count] —
封装 672-ball FineLine BGA (FBGA-672) 672-ball FC-FBGA (FineLine BGA)
Speed Grade C6 (commercial) —
工作温度 Commercial (0C to +85C) —
Process Technology 0.18-micron CMOS 0.15 µm CMOS, all-layer copper, up to 8 metal layers
Configuration Memory SRAM-based —
JTAG Support Yes (IEEE 1149.1) —
PLL Support Yes —
安装类型 Surface Mount (BGA) Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS status] Compliant
Lead-Free [DATA_NEEDED: lead-free status] Yes
Lifecycle Obsolete / EOL (per Intel/Altera product discontinuation notice) —
Logic Elements — 38,400
System Gates — 1,500,000
Macro Cells — 2,560
Maximum User I/O — 492
Core Voltage — 1.5 V
I/O Voltage Support — 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt)
Pin-to-Pin Delay — 1.55 ns (C7 speed grade)
Maximum Internal Frequency — 562 MHz
High-Speed Interface — 1 Gbps True-LVDS, LVPECL, PCML, HyperTransport
PLLs — 4
Package Dimensions — 27 x 27 mm, 1.0 mm pitch
Operating Temperature Grade — Commercial (per 'C' suffix in speed grade)

数据手册与资源

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