EP2A40F672C7 vs EP2A40F672C9 对比

详细并排对比 EP2A40F672C7 出自 Intel 和 EP2A40F672C9 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EP2A40F672C9 EP2A40F672C9 - APEX II FPGA 1.5M Gates 38400 Cells 672-BGA | Altera

EP2A40F672C9 - APEX II FPGA 1.5M Gates 38400 Cells 672-BGA | Altera

EP2A40F672C9 ⚠ 最后一次采购

规格对比

参数 EP2A40F672C7 EP2A40F672C9
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $195.00 $62.00
Family APEX II APEX II
Logic Elements 38,400 —
System Gates 1,500,000 1.5 M
Macro Cells 2,560 —
Maximum User I/O 492 —
Process Technology 0.15 µm CMOS, all-layer copper, up to 8 metal layers 0.15 µm all-layer copper, up to 8 metal layers
Core Voltage 1.5 V 1.5 V
I/O Voltage Support 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) —
Pin-to-Pin Delay 1.55 ns (C7 speed grade) —
Maximum Internal Frequency 562 MHz —
High-Speed Interface 1 Gbps True-LVDS, LVPECL, PCML, HyperTransport —
PLLs 4 —
封装 672-ball FC-FBGA (FineLine BGA) 672-BBGA, FC-FBGA (FineLine)
Package Dimensions 27 x 27 mm, 1.0 mm pitch —
安装类型 Surface Mount Surface Mount
Operating Temperature Grade Commercial (per 'C' suffix in speed grade) —
RoHS 状态 Compliant [DATA_NEEDED: RoHS status]
Lead-Free Yes —
Device Family — APEX II PLD
Logic Elements / Cells — 38,400
Macros — 2,560
User I/Os — 492
引脚数 — 672
Package Size — 27 mm × 27 mm, 1 mm ball pitch
Logic Family — CMOS
Propagation Delay — 1.55 ns
Internal Speed Grade — 366 MHz
工作温度 — 0 °C to 85 °C (commercial)
I/O Standards Supported — True-LVDS, LVPECL, PCML, HyperTransport

数据手册与资源

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