EP2A70B652C7 vs EP2A40B652C9 对比
详细并排对比 EP2A70B652C7 出自 Intel 和 EP2A40B652C9 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2A70B652C7 | EP2A40B652C9 |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $10.51 | $92.40 |
| Manufacturer | Intel (formerly Altera) | — |
| Series | APEX II | — |
| Family | APEX II (Field-Programmable Gate Array) | APEX II |
| Logic Elements (LEs) | 67200 | — |
| Typical Gates | 1140000 | — |
| Maximum User I/Os | 336 | — |
| Package Type | BGA-652 (FineLine BGA) | — |
| Package Size | 27 mm x 27 mm (approximate) | — |
| 安装类型 | Surface Mount | Surface Mount (BGA) |
| Operating Temperature Grade | Commercial (C) | — |
| Speed Grade | 7 | — |
| Core Voltage | 1.8 V | 1.5 V |
| I/O Bank Voltage (VCCIO) | 1.5V / 1.8V / 2.5V / 3.3V (bank-dependent) | — |
| Configuration Interface | JTAG, Passive Serial | — |
| 存储器类型 | Embedded SRAM blocks (ESBs) | — |
| PLL / Clock Management | Yes, dedicated PLL blocks | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Maximum System Gates | — | 1.5 M (40K logic elements) |
| Logic Elements | — | 40,160 |
| Embedded System Blocks | — | Yes (dual-port RAM, ROM, CAM) |
| Maximum User I/O Pins | — | [DATA_NEEDED: user I/O count] |
| 封装 | — | 652-pin BGA |
| Process Technology | — | 0.18 µm CMOS |
| Supply Voltage (I/O) | — | 3.3 V (multi-standard I/O supported) |
| 工作温度 | — | -40C to +85C (industrial, C9 suffix) |
| Configuration Method | — | SRAM-based, serial/parallel, JTAG IEEE 1149.1 |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, GTL+, SSTL, LVDS |
| PLL Count | — | [DATA_NEEDED: PLL count] |
| MSL 等级 | — | 3 (168 hours floor life) |