EP2A70B724I-8 vs EP2A70B724C7N 对比
详细并排对比 EP2A70B724I-8 出自 Altera 和 EP2A70B724C7N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2A70B724I-8 | EP2A70B724C7N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $119.00 | $188.00 |
| Family | APEX II | APEX II (EP2A70) |
| Logic Elements / Cells | 67,200 cells | — |
| System Gates | 3,000,000 | 3,000,000 |
| Maximum Internal Frequency | 281 MHz | 420 MHz |
| Process Technology | 0.15 µm CMOS | — |
| Core Supply Voltage | 1.5 V | 1.5 V nominal |
| I/O Supply Voltage | 3.3 V | MultiVolt (1.5V / 1.8V / 2.5V / 3.3V / 5V tolerant) |
| 引脚数 | 724 | — |
| Package Type | FCBGA (Flip-Chip Ball Grid Array) | — |
| 工作温度 | -40 °C to +100 °C (Industrial) | 0 °C to +85 °C (Commercial) |
| Peak Reflow Temperature | 220 °C (per JEDEC J-STD-020) | — |
| User I/O Banks | [DATA_NEEDED: user I/O bank count] | — |
| User I/O Pins | [DATA_NEEDED: user I/O pin count] | 536 |
| Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | — |
| Embedded Array Blocks (EABs) | [DATA_NEEDED: EAB count] | — |
| Embedded RAM | [DATA_NEEDED: total bits] | — |
| PLLs | [DATA_NEEDED: PLL count] | — |
| Configuration Method | JTAG / Passive Serial / Passive Parallel | JTAG, Passive Serial (PS), Fast Passive Parallel (FPP) |
| 安装类型 | Surface Mount | Surface Mount |
| MSL 等级 | [DATA_NEEDED: MSL level] | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Technology | — | 0.15 µm CMOS |
| Logic Cells / Logic Elements | — | 67,200 |
| Propagation Delay (typ.) | — | 2.17 ns |
| Macrocells (memory blocks reference) | — | 16 |
| 封装 | — | 724-pin FCBGA (Flip-Chip BGA) |
| Ball Pitch | — | 1.27 mm |
| Seated Height | — | 3.5 mm |
| PLL Count | — | [DATA_NEEDED: PLL count] |
| Embedded Memory | — | Embedded System Blocks (ESBs) - dual-port RAM / ROM / CAM |