EP2AGX125EF35C6G vs EP2AGX125EF35I5N 对比
详细并排对比 EP2AGX125EF35C6G 出自 Altera 和 EP2AGX125EF35I5N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Intel
EP2AGX125EF35I5N - Arria II GX FPGA 118K LE, 6x 3.125G Transceivers | Intel
EP2AGX125EF35I5N ✓ 量产中规格对比
| 参数 | EP2AGX125EF35C6G | EP2AGX125EF35I5N |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Unknown | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $0.00 | $1,390.00 |
| Product Type | Field Programmable Gate Array (FPGA) | — |
| Series | Arria II GX | — |
| Number of Logic Elements/Cells | 118143 | — |
| Total RAM Bits | 8315904 bit | — |
| User I/O Pins | 452 | — |
| Core Supply Voltage | 0.87 V to 0.93 V | 0.9 V |
| Number of LABs | [DATA_NEEDED: number of LABs] | — |
| 工作温度 | 0 °C to 85 °C (Tj) | -40C to +100C (industrial) |
| Package Type | 1152-BBGA, FCBGA | — |
| Supplier Device Package | 1152-FBGA (35 mm x 35 mm) | — |
| Package Pin Count | 1152 pin | — |
| 安装类型 | [DATA_NEEDED: mounting type] | Surface Mount (flip-chip BGA) |
| Maximum Operating Frequency | [DATA_NEEDED: maximum operating frequency] | — |
| Transceiver Count | [DATA_NEEDED: transceiver count] | — |
| Configuration Method | [DATA_NEEDED: configuration method] | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | — |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Halogen-Free Status | [DATA_NEEDED: halogen-free status] | — |
| Family | — | Arria II GX |
| Device Logic Elements | — | 118,143 |
| Combinational Logic Blocks (CLBs) | — | 124,100 |
| Logic Array Blocks (LABs) | — | 4,964 |
| User I/Os | — | 452 |
| Embedded Memory | — | 8.4 Mbit (M9K + MLAB) |
| DSP Blocks (18x18 Multipliers) | — | 252 |
| Transceivers | — | 6 (up to 3.125 Gbps) |
| PLLs | — | 4 |
| Process Technology | — | 40 nm CMOS |
| Speed Grade | — | I5 (industrial, fastest) |
| 封装 | — | 1152-ball FC-FBGA, 35 x 35 mm |
| Lead-Free / RoHS | — | Lead-Free per MS-034 |
| PCI Express Hard IP | — | Gen1 x1/x4 endpoint |
| Configuration Schemes | — | AS, PS, JTAG, FPP |