EP2S130F1020C5N vs EP2S130F1020C5 对比
详细并排对比 EP2S130F1020C5N 出自 Intel 和 EP2S130F1020C5 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2S130F1020C5N | EP2S130F1020C5 |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $1,320.00 | $4,100.00 |
| Family | Stratix II | Stratix II |
| Logic Elements | 132,540 | — |
| Adaptive Logic Modules (ALMs) | 6627 LABs (per Jotrin listing) | — |
| Total Memory Bits | 6,747,840 bits | — |
| User I/Os | 734 | — |
| Process Technology | 90 nm | 90 nm CMOS, all-layer copper |
| Core Supply Voltage (VCCINT) | 1.15 V to 1.25 V | — |
| Maximum Internal Frequency | 609.76 MHz | — |
| 封装 | 1020-ball FC-FBGA (33x33 mm) | 1020-ball FC-FBGA |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度 | Commercial (0C to +85C, C5 grade) | 0C to +85C (commercial) |
| Temperature Grade | C5 (other - per Partstack) | — |
| RoHS 状态 | [DATA_NEEDED: rohs status] | [DATA_NEEDED: rohs status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| PLLs | 4 (typical Stratix II feature) | — |
| Global Clock Networks | 16 (typical Stratix II feature) | — |
| Configuration Method | Serial/Parallel via Quartus II (typical Stratix II) | — |
| Country of Origin | Republic of Korea (per GlobalSpec) | — |
| ECCN | 3A001.a.7.a (per GlobalSpec) | — |
| Estimated EOL Date | 2023 (per GlobalSpec) | — |
| Logic Elements (LE) | — | 132,540 |
| Embedded Memory (bits) | — | 6,747,840 |
| User I/O Pins | — | 742 |
| Operating Frequency (max) | — | 609.76 MHz |
| Core Voltage | — | 1.2 V |
| Number of Multipliers (18x18) | — | 252 |
| Speed Grade | — | 5 |
| I/O Standards Supported | — | LVDS, LVTTL, LVCMOS, SSTL, HSTL |