EP2S130F1020I4RB vs EP2S130F1020C5N 对比

详细并排对比 EP2S130F1020I4RB 出自 Intel 和 EP2S130F1020C5N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2S130F1020I4RB EP2S130F1020C5N
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $875.00 $1,320.00
Family Stratix II Stratix II
Logic Elements 132,540 132,540
Number of User I/O 742 —
Number of Logic Gates 6,747,840 (equivalent gates) —
Operating Frequency (Max) 711.24 MHz —
Process Technology 90 nm 90 nm
Core Supply Voltage 1.2 V —
封装 1020-pin FC-FBGA 1020-ball FC-FBGA (33x33 mm)
安装类型 Surface Mount Surface Mount
工作温度 -40C to +100C (Industrial) Commercial (0C to +85C, C5 grade)
Speed Grade I4 —
Number of Transceivers 12 (up to 6.375 Gbps) —
Embedded Memory 6,747,840 bits (RAM blocks) —
Number of PLLs 4 (up to 16 clock pins) —
Configuration Mode JTAG / PS / PPS / EPCS / EPCQ —
MSL 等级 3 —
RoHS 状态 [DATA_NEEDED: rohs_status] [DATA_NEEDED: rohs status]
Adaptive Logic Modules (ALMs) — 6627 LABs (per Jotrin listing)
Total Memory Bits — 6,747,840 bits
User I/Os — 734
Core Supply Voltage (VCCINT) — 1.15 V to 1.25 V
Maximum Internal Frequency — 609.76 MHz
Temperature Grade — C5 (other - per Partstack)
Lead-Free — [DATA_NEEDED: lead-free status]
PLLs — 4 (typical Stratix II feature)
Global Clock Networks — 16 (typical Stratix II feature)
Configuration Method — Serial/Parallel via Quartus II (typical Stratix II)
Country of Origin — Republic of Korea (per GlobalSpec)
ECCN — 3A001.a.7.a (per GlobalSpec)
Estimated EOL Date — 2023 (per GlobalSpec)

数据手册与资源

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