EP2S15F672C4 vs EP2S15F672C5 对比
详细并排对比 EP2S15F672C4 出自 Altera 和 EP2S15F672C5 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2S15F672C4 | EP2S15F672C5 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $235.00 | $199.00 |
| Family | Stratix II | Stratix II |
| Logic Elements | 15,600 | 15,600 |
| Embedded Memory Bits | 419,328 bits | — |
| DSP Blocks | 156 (approximate, per Stratix II family) | — |
| Maximum User I/Os | 366 | — |
| 封装 | 672-ball FineLine BGA (FBGA) | — |
| Process Node | 90 nm | — |
| PLLs | 6 | — |
| 工作温度 | Commercial (0C to +85C, 'C' suffix) | Commercial (0C to +85C) |
| Speed Grade | 4 | -5 (mid-tier) |
| Configuration Method | Serial / Parallel (passive serial, fast passive parallel, JTAG) | Passive Serial / Fast Passive Parallel / JTAG |
| I/O Standards Supported | LVTTL, LVCMOS, LVDS, SSTL, HSTL (per Stratix II family) | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance per Altera product page] | Compliant (legacy lead-free version exists) |
| Lead-Free | [DATA_NEEDED: lead-free finish status] | — |
| MSL 等级 | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| Series | — | EP2S15 |
| CLBs | — | 6,240 |
| Memory Bits | — | 419,328 |
| Maximum User I/O | — | 366 |
| Operating Frequency (max) | — | 640 MHz |
| Package Type | — | 672-ball FineLine BGA (FBGA) |
| Package Dimensions | — | 27 mm x 27 mm |
| Ball Pitch | — | 1 mm |
| Process Technology | — | 90 nm CMOS |
| Voltage - Supply (VCCINT) | — | [DATA_NEEDED: VCCINT nominal] |
| 安装类型 | — | Surface Mount |