EP2S30F672C5 vs EP2S30F672C4N 对比

详细并排对比 EP2S30F672C5 出自 Intel 和 EP2S30F672C4N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2S30F672C5 EP2S30F672C4N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $155.00 $121.00
Family Stratix II —
Logic Elements 33,880 33,880
Logic Array Blocks (LABs) 1,694 —
Total RAM Bits 1,369,728 1,369,728
Embedded Multipliers (DSP blocks) 12 DSP blocks —
Maximum User I/Os 500 —
Core Voltage 1.2 V 1.2 V
Maximum Operating Frequency 609.76 MHz —
Process Technology 90 nm CMOS 90 nm CMOS
封装 672-pin FC-FBGA (flip-chip) 672-BBGA, FCBGA (FineLine BGA)
Speed Grade C5 (moderate-speed bin) C4 (Commercial, internal performance bin 4)
Operating Temperature (Commercial) 0C to 85C junction —
安装类型 Surface Mount (BGA) Surface Mount
存储器类型 TriMatrix (M512 / M4K / M-RAM) —
RoHS 状态 [DATA_NEEDED: confirmed RoHS compliance] [DATA_NEEDED: rohs status]
Series — Stratix II
Number of LABs/CLBs — 1694
Number of I/O — 500
工作温度 — 0C to +85C (Commercial, C4 grade)
Maximum Internal Frequency — 711.24 MHz
MSL 等级 — 3 (168 hours)
Lead-Free / Halogen-Free — [DATA_NEEDED: lead-free / halogen-free status]
Embedded Multipliers / DSP Blocks — [DATA_NEEDED: DSP block count]
Transceivers — N/A (Stratix II non-GX variant)
Configuration Method — Passive serial / Fast passive parallel / JTAG

数据手册与资源

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