EP2S60F1020C4N vs EP2S60F1020C3 对比

详细并排对比 EP2S60F1020C4N 出自 Intel 和 EP2S60F1020C3 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2S60F1020C4N EP2S60F1020C3
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $67.00 $1,380.00
Series Stratix II Stratix II
Family Stratix II (EP2S60) Stratix II FPGA
Logic Elements 60,440 —
Adaptive Logic Modules (ALMs) 30,220 (approx.) —
Logic Array Blocks (LABs) 3,022 3022
Embedded Memory (bits) 2,544,192 —
Embedded Memory Blocks M512/M4K/M-RAM TriMatrix memory —
DSP Blocks (18-bit x 18-bit) Up to 48 (24 per DSP block column pair typical) —
User I/Os 718 —
Maximum Core Frequency 711.24 MHz (per Arrow listing) —
Core Voltage 1.2 V 1.2 V
Process Technology 90 nm CMOS 90 nm CMOS
封装 1020-ball FC-FBGA (Fine-pitch Chip-Scale BGA) 1020-ball FC-FBGA
安装类型 Surface Mount (BGA) Surface Mount
Operating Temperature Grade Commercial (C4 suffix indicates commercial, speed grade 4) —
Configuration Modes Passive Serial, Fast Passive Parallel, JTAG —
PLLs / Clock Networks Yes - on-chip PLLs and global clock networks —
RoHS 状态 EU RoHS compliant with exemption (per Arrow listing) Compliant
Logic Elements (LEs) — 60,440
Total RAM Bits — 2,544,192 bits (2.5 Mbit)
User I/O Count — 718
Number of I/O Banks — [DATA_NEEDED: I/O banks]
DSP Blocks (18x18 multipliers) — 144 18x18 multipliers (36 DSP blocks)
PLLs — 12
Global Clock Networks — 18
Maximum Internal Frequency — 816.99 MHz
工作温度 — 0C to +85C (commercial, C3 speed grade)
Package Body Size — 33 mm x 33 mm, 1.0 mm ball pitch
Supplier Device Package — 1020-BGA
Speed Grade — C3

数据手册与资源

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