EP2S60F484C4 vs EP2S60F484C3 对比

详细并排对比 EP2S60F484C4 出自 Altera 和 EP2S60F484C3 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2S60F484C4 EP2S60F484C3
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $974.13 $92.00
Family Stratix II —
Logic Elements (LEs) 60,440 —
Adaptive Logic Modules (ALMs) 30,220 24,176
Logic Array Blocks (LABs) 3,022 —
Embedded Memory (bits) 2,544,192 —
Maximum User I/O 334 —
User I/O Banks [DATA_NEEDED: number of I/O banks] —
Process Technology 90 nm CMOS 90 nm CMOS
Core Voltage 1.2 V 1.2 V
Speed Grade C4 (commercial, moderate speed) C3
Maximum Internal Frequency 711.24 MHz (per third-party datasheet listing) —
封装 484-ball FBGA (FineLine BGA) 484-BBGA, FCBGA (FBGA-484)
安装类型 Surface Mount Surface Mount
工作温度 0C to +85C (commercial, C-grade) 0C to +85C (commercial)
RoHS 状态 [DATA_NEEDED: RoHS status per official datasheet] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] —
Configuration Memory SRAM-based, volatile (requires external config device) —
Series — Stratix II
Manufacturer — Altera (now Intel FPGA)
Logic Elements — 60,440
LABs/CLBs — 3,022
Total RAM Bits — 2,544,192
User I/O Count — 334
Package Size — 23 x 23 mm, 1.0 mm pitch
Number of PLLs — 12 (Stratix II typical)
Total Multipliers — 12 (9-bit embedded multiplier blocks)

数据手册与资源

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