EP2S60F672C3 vs EP2S60F672C4N 对比

详细并排对比 EP2S60F672C3 出自 Altera 和 EP2S60F672C4N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2S60F672C3 EP2S60F672C4N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $1,033.14 $325.00
Family Stratix II Stratix II
Logic Elements 60,440 —
Adaptive Logic Modules (ALMs) [DATA_NEEDED: ALM count] —
Total RAM Bits 2,544,192 —
Embedded Multiplier Blocks [DATA_NEEDED: 9x9 multiplier count] [DATA_NEEDED: 9x9 multiplier count]
DSP Blocks [DATA_NEEDED: DSP block count] [DATA_NEEDED: DSP block count]
User I/Os 492 —
PLLs 4 —
Global Clocks [DATA_NEEDED: global clock count] —
Process Technology 90 nm CMOS 90 nm
Core Voltage 1.2 V 1.2 V
Speed Grade C3 C4 (commercial)
封装 672-BBGA, FC-FBGA, 35 x 35 mm, 1.0 mm pitch 672-pin FC-FBGA
安装类型 Surface Mount Surface Mount
Configuration Modes PS, PPS, PPA, FPP, JTAG —
工作温度 0C to +85C (commercial) 0C to +85C (commercial)
MSL 等级 [DATA_NEEDED: MSL level] 3
RoHS 状态 [DATA_NEEDED: RoHS status] —
Logic Elements (LE) — 60,440
Adaptive Logic Modules (ALM) — 24,176
Embedded Memory (bits) — 2,544,192
Maximum User I/O — 492
Maximum Fabric Clock — 711.24 MHz
Package Type — FineLine Ball-Grid Array
Configuration Method — JTAG, Fast Passive Parallel, Active Serial
Lead-Free / RoHS — Yes (lead-free finish)

数据手册与资源

浏览全部产品 创建 BOM 获取报价