EP2S60F672C3N vs EP2S60F67214N 对比

详细并排对比 EP2S60F672C3N 出自 Intel 和 EP2S60F67214N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2S60F672C3N EP2S60F67214N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $1,175.00 $232.00
Family Stratix II Stratix II
Logic Elements (LE) 60,440 —
Logic Array Blocks (LABs) 3,022 —
Adaptive Logic Modules (ALMs) 24,176 —
Total Embedded Memory 2,544,192 bits (2.5 Mbits) —
User I/O Pins 492 —
User I/O Banks 8 —
Process Technology 90 nm CMOS 90 nm CMOS
Core Supply Voltage (VCCINT) 1.2 V —
I/O Supply Voltage (VCCIO) 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) —
Pre-Driver Supply (VCCPD) 3.3 V —
Maximum Internal Clock Frequency 816.99 MHz —
PLLs 4 —
Global Clock Networks 16 —
封装 672-pin FC-FBGA 672-ball FBGA (FineLine BGA)
安装类型 Surface Mount Surface Mount
工作温度 0C to +85C (commercial grade) -40C to +100C (industrial)
Speed Grade C3 (slower speed grade) I4 (industrial, fast)
RoHS 状态 unknown Lead-free / RoHS compliant
Lead-Free unknown —
Logic Elements — 60,440 LE
Total RAM Bits — 2,544,192 bit (2.5 Mbit)
DSP Blocks — 12
Phase-Locked Loops (PLLs) — 4
Core Voltage — 1.2 V (typical)
I/O Banks — [DATA_NEEDED: number of I/O banks]
Maximum User I/O Pins — [DATA_NEEDED: maximum user I/O count for FBGA-672]
Configuration — SRAM-based, configured via bitstream
MSL 等级 — 3 (168 hours floor life)

数据手册与资源

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