EP2SGX60EF1152C3N vs EP2SGX60EF1152I3 对比

详细并排对比 EP2SGX60EF1152C3N 出自 Intel 和 EP2SGX60EF1152I3 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2SGX60EF1152C3N EP2SGX60EF1152I3
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $2,195.00 $365.00
Family Stratix II GX Stratix II GX
Series Stratix II EP2SGX60
Logic Elements 60,440 —
Adaptive Logic Modules (ALMs) 30,220 30,220 (estimated from LEs)
Logic Array Blocks (LABs) 3022 —
Embedded Memory (bits) 2,544,192 —
Maximum User I/Os 534 —
Process Technology 90 nm CMOS 90 nm CMOS
Core Voltage (Vcc) 1.2 V —
Maximum Internal Frequency 717 MHz 717 MHz
Propagation Delay 0.40 ns —
Embedded Multipliers (18x18) [DATA_NEEDED: embedded multiplier count] —
PLLs 4 —
Transceiver Data Rate 3.125 Gbps per channel —
封装 1152-BBGA (FC-FBGA) 35 x 35 mm, 1.0 mm pitch 1152-ball FBGA, 35 mm x 35 mm, 1 mm pitch
Speed Grade C3 (commercial, -3 bin) I3 (Industrial)
工作温度 0C to +85C (commercial) -40C to +100C (Industrial, I3 speed grade)
安装类型 Surface Mount (BGA) Surface Mount (BGA)
Logic Elements (LEs) — 60,440
Equivalent Logic Cells (CLBs) — 60,440
Embedded Memory (Bits) — 2,544,192 bits (per DigiKey listing for the I4N variant)
Combinational Delay (per CLB) — 2.99 ns
Multi-Gigabit Transceivers — [DATA_NEEDED: exact count for EP2SGX60]
Maximum Transceiver Data Rate — 6.375 Gbps (per Stratix II GX family spec)
Total RAM Bits — 2,544,192 bits
Pin/Ball Count — 1152
Configuration Mode — Enhanced (EPC) - fast parallel via external memory
RoHS 状态 — [DATA_NEEDED: not in retrieved snippets]

数据手册与资源

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